Detailed explanation of Boundary Scan of ICT technology

Detailed explanation of Boundary Scan of ICT technology

In 80% and 90% of circuit board manufacturers, ICT testers require at least one test point for each circuit node. However, with the increase of device integration, stronger functions, smaller packages, more SMT processing components, the use of multilayer boards, and the increase of component density of PCBA boards, it is difficult to place a probe at each node. To increase test points, manufacturing costs will increase; At the same time, it becomes difficult to develop a test library of powerful devices, and the development cycle is prolonged. To this end, the Joint Test Organization (JTAG) issued the IEEE1149.1 test standard.

IEEE 1149.1 defines several important characteristics of a scanning device. First, four (five) pins constituting the test access port (TAP) are defined: TDI, TDO, TCK, TMS, (TRST). Test mode selection (TMS) is used to load control information; Secondly, several different test modes supported by TAP controller are defined, mainly including external test, internal test and running test; Finally, the Boundary Scan Description Language is proposed. BSDL describes the important information of scanning devices. It defines pins as input, output and bidirectional types, and defines the mode and instruction set of TAP.

Each pin of the device with boundary scan is connected to a unit of a serial shift register (SSR), which is called a scan unit. The scan units are connected to form a shift register chain to control and detect device pins. Its specific four pins are used to complete the test task.

Connect the scan chains of multiple scanning devices through their TAPs to form a continuous boundary register chain. Add TAP signal to the chain head to control and detect the pins of all devices connected to the chain. This virtual contact replaces the physical contact of the needle bed fixture on each pin of the device, and virtual access replaces the actual physical access, removing a large number of test pads that occupy PCB board space, reducing the manufacturing costs of PCB and fixture.

As a test strategy, when designing for testability for PCB boards, special software can be used to analyze circuit dots and devices with scanning function, and decide how to effectively place a limited number of test points without reducing test coverage, so as to reduce test points and test pins most economically.

The boundary scan technology solves the difficulty of not adding test points. More importantly, it provides a simple and fast method to generate test graphics. Using software tools, you can convert BSDL files into test graphics, such as Teradyne's Victory, GenRad's Basic Scan and Scan Path Finder. Solve the difficulty of writing complex test libraries.

The TAP access port can also be used for online programming (In System Program or On Board Program) of CPLD, FPGA and Flash Memory.