Overview of PCBA electrical stress test methods

Quality control in mass production and prototyping has a common set of important tasks: the need for PCB testing. The specific set of tests you need to perform in a PCBA depends on its application area, desired service conditions, and, of course, the relevant industry standards for your product. Some basic testing and inspection tasks may be required to be performed on your PCB/PCBA during the manufacturing and assembly process, and it is recommended that these tests be performed, at the very least, to ensure continuity, accurate assembly, and simply to find any obvious defects that may require rework.

High reliability applications may require more than simple electrical testing and inspection, both during the manufacturing/assembly process, once the prototype is in the hands of the design team, and/or by an external test laboratory. Electrical stress testing is just one of the possible tests that should be performed in high reliability components to ensure that PCbas can withstand harsh electrical conditions.

Fundamentals of electrical pressure testing

First of all, whenever something like testing comes up, new designers may think that they forgot something, or that they have to plan for some extreme testing before they can accept a board from the manufacturer. You'll be doing a lot of functional testing, but you don't need to worry about specific stress limits in the quantified boards unless you're being reviewed by a standards body (e.g. UL), your product has regulatory requirements, and you're transitioning to high capacity.

Don't overthink this if you're prototyping, or if you're only producing a small number of disposable boards. Hobby projects, simple prototypes, demo board projects, or one-time projects are generally not suitable for electrical stress testing. There are some number 1 exceptions, such as highly specialized aerospace products (satellites, drones, etc.). If your board will not be deployed in areas or conditions where there is a risk of extreme electrical stress, you may not need an electrical stress test.

By the way, what is the new technology in electrical stress testing, and what exactly is "pressure"? Some of the main stress testing methods may fall into the following areas:

Electrical overs tress test

Electrostatic discharge (ESD) test

Environmental pressure screening

Accelerated life test

The idea is to identify issues that cause unexpected breakdowns in the board, or simply quantify when the board breaks down (or both). While other quality control tests may be performed during the manufacturing process, we'll focus on the list above for now.

Electrical overload (EOS) test

This is sometimes confused with ESD because they are both forms of overstress on components. The EOS test is probably the simplest electrical stress test you can perform: the components are essentially overloaded, and the DUT is monitored until the device fails. This is usually done at the wafer level or at the individual device level, just to quantify when a device will fail and how it fails.

If you are looking at the ratings in the data sheet, you will see recommendations based on the EOS test results for individual components. These ratings are defined with a margin of safety, so you may be able to exceed these values. What you don't see is system-level electrical overload. This is where you need to manually overload the system at each interface and power supply, and you need to monitor performance or output to ensure that the device can withstand any expected overload.

Electrostatic discharge (ESD) test

This test is exactly what it is called: it tests how well PCbas can withstand ESD events. When an ESD event occurs, your PCBA will interact with very strong electrical pulses that may reach currents above 10,000 V and exceed a few amperes. If such an event is not transferred back to the safety grounding in the system, it may damage the component. ESD circuits are designed to absorb and/or divert ESD pulses away from components and into a safe grounding area in the system. Certain digital interfaces (such as the IEEE 802.3 standard on Ethernet PHY) have their own ESD requirements that must be met at the component level.

JEDEC distinguishes ESD at the component level and system level. PCB designers need to think about what happens at the system level because this is the area they can control.

Where a system-level ESD is likely to occur. Exposed IO and connectors are obvious locations where ESD events can propagate electrical impulses into the system and potentially damage components.

A system-level ESD event occurs within a PCBA and may affect multiple components, resulting in one of the following outcomes:

There is no problem with the system continuing to work

The system has a failure/lock (soft failure), but no physical failure.

Physical damage to the system (hard failure)

Various industry standards beyond the IPC standard require the ability of equipment to withstand electrostatic discharge. The specific test method depends on the standard used for your product (e.g. IEC 62368-1/IEC 61000, ISO 10605 for automobiles, DO-160 for avionics, etc.). Refer to the relevant safety standards for your product and industry to determine the level of ESD protection required for your product.

Environmental stress screening (ESS) tests

These tests are designed to closely simulate the ideal deployment environment for the appliance. ESS testing may involve the application of thermal cycling, drop testing, vibration testing, thermal/mechanical shock testing, and any other environmental or mechanical exposure to which the equipment is expected to be subjected during operation. More specialized testing methods might involve crash testing, pressure and humidity testing, or even altitude testing. Highly reliable systems need to withstand all of these environmental factors during electrical operation, so multiple tests are often required to ensure reliability.

Functional tests are also performed before, during, and after these tests to fully determine whether the design will fail and whether functionality will be compromised. These tests not only looked at electrical stress, but also verified functionality in a variety of pressure situations, which could include electrical overstress and even ESD. Because this is usually a combination of professional tests that need to be performed, the rigorous evaluation is performed by the design team rather than the manufacturer.

Accelerated life test

This refers to a set of possible tests designed to determine the approximate useful life of the new equipment. Accelerated life tests are often lumped together as "burn-in tests," although there are many variations on these tests. The accelerated life test can be divided into the following aspects:

Burn-in testing: A method of using statistical techniques to determine which components and/or components will fail early.

High Accelerated Life Testing (HALT) : The goal here is to stress the device until it fails during severe overrun. This simulates excessive operation under real environmental conditions where the device is deployed.

Highly Accelerated Stress testing (HAST) : Similar to HALT, in that designs are stressed to complete failure.

Highly accelerated stress testing (HASS) : Use the same ambient stress as HASS, but at a lower level, and usually after completing a full HALT test.

Any of these life/stress tests can be carried out in accordance with the other test methods described above, provided appropriate testing rooms and equipment are available. This combination of tests can be highly specialized, but they are critical to determining the useful life of electronics and identifying failure mechanisms.

Fault analysis

These electrical stress tests are designed to determine the limits of the equipment and to assess whether it can withstand the environmental conditions during operation. If you find that the design cannot withstand the expected stress level and fails, some failure analysis is required to determine the root cause of the equipment failure. Failures can occur at the component level, board level, or both, so some forensic investigation is required to determine the failure mechanism.