PCB design: visual signal eye map, attenuation know well

The previous several articles talked about the serial bus pre-weight and equilibrium theory, conceptual things are more, if you are not engaged in signal integrity simulation and other related staff, there will be certain difficulties in understanding. A lot of attention to Mr. High-speed public number are engaged in high-speed PCBdesign (Layout) of the small partner, signal processing theory may not help these friends in their daily work is not too much, these friends may pay more attention to the topic related to wiring.

Colleagues of PCB design often ask me, what is the longest line length of PCIe or 10G optical port on the board? Does a signal with a less high speed, such as USB2.0, go a long way? How high is the speed, and you have to pay special attention to the loss of the line? The core of these problems still involves the relationship between high-speed signal rate and transmission line loss. If we have a basic understanding of the attenuation of signals of different rates through the transmission line, we can do a basic evaluation of the wiring length.

Before answering these questions, we should have some understanding of the loss of signals of different frequencies after passing a length of transmission line. Do you think a digital signal with a transmission rate of 5Gbps (without any pre-weighted or equalized processing) can be opened after a 15inch transmission line (ordinary plate), and 8G? In order to solve your doubts, I made the following simulation:

We assume that both the driving and receiving devices of the communication system are ideal models, which means that the driving and receiving are well matched, and the signal is not affected by other interference items except the loss of the transmission line. Assume that the medium of the transmission line is ordinary FR4, the line width is 5mil, the impedance is 50ohm, and the line length is 15 inches. First, let's look at the insertion loss curve of the channel:

It can be seen from the insertion loss curve that the channel loss is still very large, reaching -7.9dB at 2.5G, which is translated into amplitude, about 0.4, that is, at this frequency, the amplitude loss of the signal is 60%. Let's look at what happens to signals of different rates as they pass through this channel.

The sending end is an ideal PRBS signal, the peak-to-peak value of the sending end signal is 1V, and the rise and fall time is 10ps. We have simulated the signals with speeds of 1G, 2.5G,5G,8G,10G and 25G respectively. After passing the transmission line of 15inch:

The statistical comparison of eye height and eye width is as follows:

As can be seen from the above table, with the increase of signal frequency, the impact of loss becomes more and more significant. As to how big this effect is, we can use the table above for a rough estimate.

More true users may have doubts, you said so much, I just want to know when I am in the wiring high-speed line in the end can go how long, you can give an accurate value. When confronted with these questions, Mr. High-speed cannot give clear answers. Well,it depends... ... From the transmission channel, the line length is only one of the factors affecting the loss, there are many key factors affecting the loss of the channel, such as the plate we choose, the type of layer hole, the number, the type of copper foil used, the line width and thickness, and so on. For high-speed serial signals, different chips also have different signal processing capabilities, namely the so-called pre-weighting and equalization capabilities are not the same, since the chip performance is different, we can not be generalized in the evaluation of the transmission channel. The best method is to get the chip model for simulation evaluation, comprehensive consideration of the impact of these factors on the signal, which is the value of SI engineers.

The outer copper skin of the circuit board is bonded together by high temperature and high pressure vacuum and melted PP, and the uranium foil on the hair surface is combined with the colloidlike resin. After fully curing, it is closely bonded together, which is not easy to stratify. The copper plating in the depth control area only deposits a layer of copper on the surface of the substrate in the depth control area by electroplating, because there is no adhesive involved in the deposition of copper, which is the binding force of the copper and PCB Is far less than the binding force of copper foil and resin on the surface when pressed. In reflow welding, affected by thermal shock, layered bubbling will occur, so the case occurred.