How to solve signal reflection in high speed PCB board design

In a high speed PCB, wiring is more than just connecting two points. As a qualified engineer, wiring is a hybrid knowledge carrier including resistance, capacitance and inductance. The signal line will have reflection in the transmission process. It must be understood that the reflection of the load end depends on the Z of the transmission line and the Z of the load.

The reflected size of the signal is measured by the reflection coefficient KR. The reflection coefficient of the load side is KRL=(ZL -- Z0)/(ZL+Z0). For open-circuit load, KRL=1; For short-circuited loads, KRL=-1 is visible, and for open and short-circuited loads, the signal is 100% reflected back. A negative KRL indicates that the reflected signal is in the opposite direction from the original signal. Similarly, the magnitude of the signal reflection at the source is expressed by the reflection coefficient at the source: KRS=(ZS -- Z0)/(ZS+Z0).

If the standard output level of the driver is 0.2V and the current is 24mA, its output impedance ZS is about 8.3Ω. If the input impedance ZL of the load is greater than 100KΩ and much larger than Z0 (about 67Ω), the reflection coefficient of the load end is KRL=1, and the signal is 100% reflected at the load end. The source reflection coefficient is KRS=-0.78. Bioneng belongs to Qinji Group, is the leading electronic industry service platform in China, providing online components, sensor procurement, PCB customization, BOM, material selection and other electronic industry supply chain solutions, one-stop to meet the comprehensive needs of small and medium-sized customers in the electronics industry.

The following is a detailed analysis of the driver generated from a 3.5V to 0.2V signal reflection process.

The first reflection: the driver voltage is 3.3V. According to the voltage division principle composed of ZS and Z0, the signal generated on Z0 is △V=-2.94V, and the signal voltage at the source end is VS=O.56V. The reflection coefficient at the load end is 1. When the signal reaches the load, VL=3.5-2.94-2.94=-2.38V.

The second reflection: the signal at the source end starts at 0.56V, and the second reflection occurs when the -2.94V signal reaches the source end. The reflected voltage is: VR=KPS*△V =-0.78*(-2.94)=2.29V. So the source voltage becomes VS=0.56+ (-2.94) +2.29=-0.09V.

Third reflection: When the second reflection signal reaches the load terminal, the load terminal voltage changes to VL =-2.38+2.29+2.29=2.2.V

On such impedance mismatched transmission lines, the signal bounces back and forth in this way, decreasing in amplitude with each reflection until it finally disappears. The vertical lines on the left and right represent the voltage at the source and the load, respectively, while the diagonal lines indicate the voltage of the transmitted and reflected signals. It can also be used to represent the specific reflection process of the signal, with one representing the source side signal and one representing the load side signal. It can be seen that after 5 cycles, the signal transmitted to the load end drops below the input threshold value, and the transmission delay is generally between 6 -- 16ns/m. If the transmission delay tPD=10ns/m, then the delay through a 0.15m transmission line is about 1.5ns. Then the signal can be considered valid after about 13.5ns has been transmitted.

Six-ply plate

If the density of the components on the 4-ply plate is relatively high, it is better to use the 6-ply plate. However, the shielding effect of the electromagnetic field is not good enough for some laminated schemes in the design of 6-layer board, which has little effect on the reduction of the transient signal of the power busbar. Two examples are discussed below.

In the first case, the power supply and the ground are placed in the second and fifth layers respectively. Due to the high copper impedance of the power supply, it is very unfavorable to the control of common mode EMI radiation. However, from the point of view of impedance control of the signal, this method is very correct.

The second example places the power supply and ground in layers 3 and 4, respectively. This design solves the problem of copper-clad impedance of the power supply. Due to the poor electromagnetic shielding performance of layers 1 and 6, differential mode EMI is increased. If the number of signal wires on the two outer layers is minimal and the line length is very short (less than 1/20 of the highest harmonic wavelength of the signal), then this design can solve the differential mode EMI problem. The suppression of differential mode EMI is particularly good when the non-component and non-wireline areas on the outer layer are filled with copper and the copper-covered areas are grounded (at intervals of 1/20 wavelength). As mentioned above, the copper-laying area should be connected to multiple points of the internal connecting strata.

General purpose high performance 6-story board designs generally distribute layers 1 and 6 as strata, and layers 3 and 4 as power and ground. Because there are two layers of microstrip signal line between the power layer and the ground layer, EMI suppression ability is excellent. The drawback of this design is that there are only two layers of wiring. As described earlier, if the outer wiring is short and copper is laid in the non-wiring area, the same stacking can be achieved with a conventional 6-ply board.

Another 6-layer board layout is signal, ground, signal, power, ground, signal, which enables the environment required for advanced signal integrity design. The signal layer is adjacent to the grounding layer, and the power layer is paired with the grounding layer. Obviously, the downside is that the layers are stacked unevenly.

This usually causes problems in manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After filling with copper, if the copper coating density of the third layer is close to that of the power layer or grounding layer, this board can be loosely counted as a structurally balanced circuit board. The copper filling area must be connected to the power supply or grounded. The holes are still 1/20 wavelength apart, so you don't have to connect them everywhere, but ideally you should.