Impedance matching in high speed PCB design

Impedance matching means that when energy is transferred, the load impedance is required to be equal to the characteristic impedance of the transmission line. In this case, the transmission does not produce reflections, indicating that all the energy is absorbed by the load. Otherwise there is a loss of energy in transmission. In high speed PCB design, impedance matching is related to signal quality.

When does PCB routing need impedance matching?

It is not mainly to look at the frequency, but the key is to look at the edge steepness of the signal, that is, the rise/fall time of the signal. It is generally believed that if the rise/fall time of the signal (according to 10% ~ 90%) is less than 6 times the wire delay, it is a high-speed signal, and we must pay attention to the problem of impedance matching. Generally, the conductor delay is 150ps/inch.

Characteristic impedance

When a signal travels along a transmission line, if the signal travels at a consistent speed all over the line and the capacitance per unit length is the same, then the signal will always see exactly the same instantaneous impedance as it travels. Since the impedance remains constant throughout the transmission line, we give a specific name to denote this characteristic or characteristic of a particular transmission line, called the characteristic impedance of the transmission line. Characteristic impedance is the value of the instantaneous impedance seen by the signal as it travels along the transmission line. Characteristic impedance is related to PCB wire layer, PCB material (dielectric constant), wire width, distance between wire and plane and other factors, and has nothing to do with wire length. Characteristic impedance can be calculated using software. In high-speed PCB wiring, the linear impedance of digital signal is generally designed to be 50 ohms, which is an approximate number. Coaxial cable is generally defined as 50 ohms in base band, 75 ohms in frequency band, and 100 ohms for twisted wire (difference).

Common impedance matching mode

1, series terminal matching

Under the condition that the impedance of the source end is lower than the characteristic impedance of the transmission line, a resistance R is connected in series between the source end of the signal and the transmission line, so that the output impedance of the source end matches the characteristic impedance of the transmission line, and the signal reflected back from the load end is inhibited from reflecting again.

Matching resistance selection principle: The sum of the matching resistance value and the output impedance of the driver is equal to the characteristic impedance of the transmission line. Common CMOS and TTL drivers have output impedances that vary with the level of the signal. Therefore, it is impossible to have exactly the right matching resistance for a TTL or CMOS circuit, so you have to compromise. The network with chain topology is not suitable for series terminal matching, all the load must be connected to the end of the transmission line.

Series matching is the most common terminal matching method. It has the advantage of low power consumption, does not impose additional DC load on the driver, does not introduce additional impedance between the signal and the ground, and requires only one resistance element.

Common applications: impedance matching of CMOS and TTL circuits in general. USB signals are also sampled this way to do impedance matching.

2. Parallel terminal matching

When the impedance of the source is very small, the input impedance of the load is matched with the characteristic impedance of the transmission line by adding the parallel resistance, so as to eliminate the reflection of the load end. The realization form is divided into single resistance and double resistance two forms.

Matching resistance selection principle: when the input impedance of the chip is very high, for the single resistance form, the parallel resistance value of the load side must be close to or equal to the characteristic impedance of the transmission line; For the dual resistance form, the value of each parallel resistance is twice the characteristic impedance of the transmission line.

The advantage of parallel terminal matching is simple and easy, but the obvious disadvantage is that it brings DC power consumption. The DC power consumption of single-resistance mode is closely related to the duty ratio of signal. The dual resistance mode has DC power consumption no matter the signal is high level or low level, but the current is half less than the single resistance mode.

Common applications: high speed signal applications.

(1) SSTL drives such as DDR and DDR2. In single resistance form, parallel to the VTT (generally half of the IOVDD). The parallel matching resistance of DDR2 data signals is built in the chip.

(2) TMDS and other high-speed serial data interface. In the form of a single resistance, the receiving device is connected in parallel to IOVDD, and the single-end impedance is 50 ohms (100 ohms between differential pairs).