Signal reflux and cross division in high speed PCB

Here is a simple "scenario", combined with the following figure to introduce ground reflux and power reflux and some cross-segmentation problems. For the convenience of drawing, enlarge the spacing of layers.

IC1 is the signal output end, IC2 is the signal input end (for the simplified PCB model, it is assumed that the receiving end contains the underlying resistance) and the third layer is the stratum. Both IC1 and IC2 are from the third layer. The upper right corner of the top layer is a power plane connected to the positive terminal of the power supply. C1 and C2 are the decoupling capacitors of IC1 and IC2, respectively. The power supply and ground of the chip shown in the figure are the power supply and ground of the signal sending and receiving terminals.

At low frequencies, if S1 outputs a high level, the entire current loop is the power supply connecting to the VCC power plane through the wire, then entering IC1 through the orange path, then exiting from S1, entering IC2 along the second layer of wire through the R1 end, then entering the GND layer, returning to the negative terminal of the power supply through the red path.

However, at high frequency, the distribution characteristics presented by the PCB will have a great impact on the signal. We often say that the ground reflux is often encountered in high frequency signals. When there is an increased current in the S1 to R1 signal line, the external magnetic field changes rapidly, causing the nearby conductor to induce a reverse current. If the ground plane of the third layer were a complete ground plane, there would be a blue dashed line indicating the current on the ground plane; If there is a complete power plane at the TOP level, there will also be a backflow at the top level along the blue dashed line. At this point, the signal loop has the smallest current loop, the smallest energy radiated outward, and the smallest ability to couple the external signal. (The skin effect at high frequencies also radiates the least outward energy. The principle is the same.)

Because the high frequency signal level and current change quickly, but the change period is short, the energy required is not very large, so the chip and the nearest decoupling capacitor to the chip power. When C1 is large enough and the reaction is fast enough (with a very low ESR value), chip capacitors are usually used. The ESR of porcelain capacitor is much lower than that of tantalum capacitor. , the orange path in the top layer and the red path in the GND layer can be regarded as non-existent (there is a current corresponding to the power supply of the whole board, but not the current corresponding to the indicated signal).

Thus, according to the environment constructed in the figure, the entire path of the current is: from the positive terminal of C1 -> VCC-&gt of IC1; S1-> L2 Signal cable -> R1-> GND-&gt of IC2; Through hole -> $path for GND layer -> Through hole -> Capacitance negative terminal. As you can see, the vertical direction of the current has a brown equivalent current, which induces a magnetic field, and the torus is easily coupled to external interference. If the signal is a clock signal and there is a set of 8-bit data lines in parallel, powered by the same power supply on the same chip, the current return path is the same. If the level of the data line is flipped in the same direction at the same time, it can induce a large reverse current on the clock. If the clock line is not well matched, this crosstalk can be fatal to the clock signal.

The intensity of the cross talk is not proportional to the absolute value of the high and low levels of the interference source, but to the rate of current change of the interference source. For a purely resistive load, the cross talk current is proportional to dI/dt=dV /(T10%-90%*R). In the formula, dI/dt (current change rate), dV(interference source swing), and R(interference source load) refer to the parameters of the interference source. (If the load is capacitive, dI/dt is inversely proportional to the square of T10%-90%.) . It can be seen from the formula that the crosstalk of the signal at low speed is not necessarily smaller than that of the signal at high speed. That is to say: 1kHZ signal is not necessarily a low speed signal, to consider the situation along. For the signal along very steep, is contains many harmonic components, at each frequency multiplier has a large amplitude. Therefore, it is important to be careful when choosing components. Do not choose a chip with fast switching speed, which will not only cost more, but also increase crosstalk and EMC problems.