Impedance matching in DI PCB design

Impedance matching in DI PCB design

Impedance matching means that when transmitting the source, the load impedance must equal the characteristic impedance of the transmission line. In this case, the transmission will not reflect, indicating that all sources have been absorbed by the load. Instead, there is a source loss during transmission. In HDI PCB design, impedance matching is related to signal quality.https://www.kingfordpcb.com/yuan.php

It is not primarily determined by frequency, but the key is the steepness of the signal, i.e. the time the signal goes up/down. It is generally considered that if the signal's rise/fall time (based on 10% to 90%) is less than 6 times the line delay, it is a high speed signal and attention must be paid to impedance matching. Wire delay is usually set to 150ps/inch.

During the transmission of the signal along the transmission line, if there is a consistent signal propagation speed everywhere along the transmission line and the capacitance per unit length is the same, the signal will always see a perfectly consistent instantaneous impedance as it travels. Since the impedance remains constant throughout the transmission line, we use a specific name for the characteristic or the characteristic of a particular transmission line, which is called the characteristic impedance of a transmission line. Characteristic impedance is the instantaneous impedance value when the signal is seen along the transmission line. The characteristic impedance is dependent on the board where the PCB leads are located, the material (dielectric constant) used by the PCB, the width of the wire, and the distance between the conductor and the pad, independent of the length of the wire. Software can be used to calculate the characteristic impedance. In HDI PCB designs, the linear impedance of the digital signal is usually designed to be 50 ohm, which is an approximation. Typically, coaxial cable has a 50 ohm base band, 75 ohm frequency band, and 100 ohm for twisted pair (differential).

Impedance matching in HDI PCB design under the condition that the impedance of the signal source is lower than the characteristic impedance of the transmission line, the series resistance R between the signal source and the transmission line, so that the output impedance of the signal source matches the characteristic impedance of the signal source. The transmission line reflects the signal from the load in order to inhibit the occurrence of a second reflection.

Matching resistance selection principle: The sum of the matching resistance value and the output impedance of the driver is equal to the characteristic impedance of the transmission line. The output impedance of common CMOS and TTL drivers will vary with the signal level. Therefore, for TTL or CMOS circuits, it is impossible to have a very correct matching resistance, and only a compromise can be considered. Signal networks with chain topology are not suitable for series terminals. All loads must be connected to the end of the transmission line.

Tandem terminal matching is the most common. Its advantages are low power consumption, no additional DC load on the driver, no additional impedance between the signal and the ground, and only one resistive element is required.

Common application: Impedance matching of universal CMOS and TTL circuits. USB signals are also sampled in this way for impedance matching.

Impedance matching in HDI PCB design

When the impedance of the signal source is very small, the input impedance of the load can be matched to the characteristic impedance of the transmission line by increasing the shunt resistance to eliminate the reflection of the load. The realization form is divided into single resistance and double resistance two forms.

Matching resistance selection principle: When the input impedance of the chip is very high, for a single resistance type, the concurrent resistance value of the load side must be close to or equal to the characteristic impedance of the transmission line; For the dual resistance type, the value of each parallel resistance is twice the characteristic impedance of the transmission line.

The advantage of parallel terminal matching is simple and easy, but the obvious disadvantage is that it brings DC power consumption. The DC power consumption of the single resistance method is closely related to the duty ratio of the signal. The dual-resistance method has DC power consumption regardless of high or low signal, but the current is half less than that of the single-resistance method.

Common applications: Most applications with high speed signals.

1.SSTL driver, such as DDR and DDR2. It takes the form of a single resistor and is connected in parallel to the VTT (usually half of the IOVDD). Parallel matching resistors for DDR2 data signals are built into the chip. 2. High-speed serial data interface, such as TMDS. It takes the form of a single resistor and is in parallel with the IOVDD at the receiving device with a single-ended impedance of 50 ohm (100 ohm between differential pairs).