Key Points of High Speed FPGA Design Circuit Board

Key Points of High Speed FPGA Design Circuit Board

In circuit board design, in order to minimize crosstalk, several guidelines can be followed for the routing of microstrip lines and striplines. For the double strip line layout, the wiring is carried out on two layers of inner plates, with a voltage reference plane on both sides. At this time, it is better to use the orthogonal wiring technology for all the conductors adjacent to the plates, so as to maximize the thickness of the dielectric material between the two signal layers, minimize the distance between each signal layer and its adjacent reference plane, and maintain the required impedance.

Microstrip or stripline routing guidelines

The line trace spacing shall be at least three times the thickness of the dielectric layer between the wiring layers of the circuit board; It is best to use a simulation tool to simulate its behavior in advance.

In order to minimize the influence of common mode noise, the critical high-speed network is replaced by a differential topology. Within the design limit, try to match the positive and negative pins of the differential signal path.

Reduce the coupling effect of single end signals, leave appropriate spacing (more than three times the trace width), or route on different boards (adjacent layers are orthogonal to each other). In addition, the use of simulation tools is also a good way to meet the spacing requirements.

Reduce the parallel length between signal termination signals to the minimum.

Simultaneous conversion noise

When the clock and I/O data rate increase, the number of output transitions decreases correspondingly, and the transient current during the discharge and charging of the signal path increases accordingly. These currents may cause board level ground bounce, that is, the ground voltage/Vcc rises/falls instantaneously. The large transient current of non ideal power supply will cause the instantaneous drop of Vcc (Vcc drop or sag). Here are some good board design rules to help reduce the impact of these simultaneous conversion noises.

Configure unused I/O pins as output pins and drive them with low voltage to reduce ground bounce.

Minimize the number of simultaneous conversion output pins, and make them evenly distributed in the entire FPGA I/O part.

When high edge rate is not required, low slew rate is selected for FPGA output.

The Vcc is inserted between the grounding planes of the multilayer board to eliminate the influence of high-speed traces on each layer.

Using all the board layers for Vcc and grounding can minimize the resistance and inductance of these planes, thus providing a low inductance source with lower capacitance and noise, and returning logic signals on the signal layers adjacent to these planes.

Pre emphasis and balance

The high-speed transceiver capability of the most advanced FPGAs makes them efficient programmable system level chip components, and also brings unique challenges to circuit board designers. A key problem, especially related to the layout, is the frequency related transmission loss, which is mainly caused by skin effect and dielectric loss. When the high-frequency signal is transmitted on the conductor surface (such as PCB trace), the skin effect will occur due to the self induction of the wire. This effect reduces the effective conductive area of the wire and weakens the high-frequency component of the signal. The dielectric loss is caused by the capacitive effect of the dielectric material between the layers. Skin effect is proportional to the square root of frequency, while dielectric loss is proportional to frequency; Therefore, dielectric loss is the main loss mechanism of high-frequency signal attenuation.

The higher the data rate, the more serious the skin effect and dielectric loss. For 1Gbps systems, the reduction of signal level on the link is acceptable, but not for 6Gbps systems. However, the current transceivers have transmitter pre emphasis and receiver equalization functions, which can compensate for the distortion of high-frequency channels. They can also enhance signal integrity and relax the limit of trace length. These signal conditioning technologies extend the life of standard FR-4 materials and can support higher data rates. Due to the signal attenuation in the FR-4 material, the allowable trace length is limited to a few inches when operating at 6.375Gbps. The pre weighting and equalization functions can extend it to more than 40 inches.

Some high-performance FPGAs integrate programmable pre emphasis and equalization functions, such as Stratix II GX devices, so they can use FR-4 materials, relax layout restrictions such as maximum trace length, and reduce the cost of circuit boards. The pre emphasis function can effectively improve the high-frequency component of the signal. The 4-tap pre emphasis circuit in Stratix II GX can reduce the scattering of signal components (space spreading from one bit to another). The pre emphasis circuit can provide a maximum of 500% pre emphasis, and each tap can be optimized to a maximum of 16 stages according to the data rate, trace length and link characteristics.

The Stratix II GX receiver contains a gain stage and linear equalizer to compensate for signal attenuation. In addition to the input gain stage, the device also allows circuit board designers to have a maximum 17dB equalization level, which can use any of the 16 equalizer stages to overcome the problem of board loss. Equalization and pre emphasis can be used in concert environments or individually to optimize specific links.

When the system is running, or when the card is configured after it is inserted into the backplane or other chassis, the designer can change the pre emphasis and equalization levels in the Stratix II GX FPGA. This gives the system designer the flexibility to automatically set the pre emphasis and equalization levels to predetermined values. In addition, these values can also be dynamically determined according to which slot the board is inserted into the chassis or backplane.

EMI problems and debugging

The electromagnetic interference caused by the printed circuit board is directly proportional to the change of current or voltage with time and the series inductance of the circuit. Efficient circuit board design may minimize EMI, but may not eliminate it completely. Eliminating "intruder" or "hot" signals, and properly referencing the ground plane to send signals, can also help reduce EMI. Finally, the use of surface mount components, which are common in the market today, is also a way to reduce EMI.

Debugging and testing complex high-speed PCB designs has become increasingly difficult, because some traditional board debugging methods, such as test probes and "Bed of nails" testers, may not be applicable to these designs. This new high-speed design can make use of JTAG test tool with in system programming function and built-in self-test function that FPGA may have. Designers should use the same guidelines to set the JTAG Test Clock Input (TCK) signal as the system clock. In addition, it is also important to minimize the JTAG scan chain trace length between the test data output of one device and the test data input of another device.

To successfully design with embedded high-speed FPGA, we need abundant high-speed board design practice and a full understanding of FPGA functions, such as pin arrangement, circuit board material and stack, circuit board layout, and terminal mode. The proper use of pre emphasis and equalization functions of the built-in transceiver is also important. The above points can be combined to achieve a reliable design with stable manufacturability. Careful consideration of all these factors, together with correct simulation and analysis, can minimize the possibility of accidents in the circuit board prototype, and will help reduce the pressure on the circuit board development project. Circuit board assembly, circuit board design, circuit board processing manufacturers introduce the key points of high-speed FPGA design circuit board in detail.