PCB design experience sharing of a hardware expert

PCB design experience sharing of a hardware expert

1： Cost savings

Phenomenon 1: It doesn't matter how large the resistance of these pull-up/pull-down resistors are, let's choose an integer of 5K

Comments: There is no 5K resistance in the market. The closest one is 4.99K (accuracy 1%), followed by 5.1K (accuracy 5%). Its cost is 4 times and 2 times higher than 4.7K (accuracy 20%). The resistance values with 20% accuracy are only 1, 1.5, 2.2, 3.3, 4.7 and 6.8 (including integral multiples of 10); Similarly, the capacitance with 20% accuracy only has the above values. If other values are selected, higher accuracy must be used, and the cost will be multiplied several times, but no benefits can be brought.

Phenomenon 2: What color is the indicator light on the panel? I think blue is special, so choose it

Comments: Other colors, such as red, green, yellow and orange, regardless of size (less than 5MM), have been mature for decades, and the price is generally less than 50 cents, while blue is something that has been invented in recent three or four years. The technical maturity and supply stability are poor, but the price is four or five times higher. At present, the blue indicator light is only used for occasions that cannot be replaced by other colors, such as displaying video signals

Etc.

Phenomenon 3

Comments: The gate circuit of 74XX is only a few cents, while CPLD costs at least tens of dollars (GAL/PAL is only a few dollars, but the company does not recommend it). The cost has been increased by N times. It also adds several times of work to production, documentation and other work.

Phenomenon 4: Our system requirements are so high, including MEM, CPU, FPGA and all other chips should choose the fastest

Comment: In a high-speed system, not every part works at a high-speed state. Every time the speed of a device increases by a level, the price will almost double. In addition, it also brings great negative effects on signal integrity.

Phenomenon 5: The PCB design requirements of this board are not high, so use thinner lines to automatically cloth

Comments: Automatic wiring will inevitably occupy a larger PCB area and generate many times more vias than manual wiring. Among products in large batches, the factors considered by PCB manufacturers for price reduction, apart from business factors, are the line width and the number of vias. They respectively affect the yield of PCB and the consumption of drill bits, saving the cost of suppliers, and thus finding reasons for price reduction.

Phenomenon 6: As long as the program is stable, long code and low efficiency are not critical

Comment: CPU speed and memory space are bought with money. If you spend a few more days to improve program efficiency when writing code, the cost saved by reducing CPU frequency and memory capacity is absolutely cost-effective. The CPLD/FPGA design is similar.

2： Low power design

Phenomenon 1: Our system is powered by 220V, so we don't care about power consumption

Comment: The low power consumption design is not only to save power, but also to reduce the cost of power module and cooling system. The reduction of current also reduces the interference of electromagnetic radiation and thermal noise. As the temperature of the device decreases, the life of the device will be extended accordingly (the life of the semiconductor device will be shortened by half for every 10 ℃ increase in the operating temperature)

Phenomenon 2: These bus signals are pulled with resistance, which makes me feel relieved

Comment: There are many reasons why signals need to be pulled up and down, but not all of them need to be pulled up and down. Pull up and down the resistance to pull a simple input signal, and the current will be less than tens of microamps. But pull a driven signal, and the current will reach milliampere level. Today's systems often use 32 bits of address data, and possibly 244/245 isolated buses and other signals. If you pull up, the power consumption of several watts will be consumed by these resistors (don't treat the power consumption of these watts with the concept of 80 cents per kilowatt).

Phenomenon 3: How to deal with these unused I/O ports of CPU and FPGA? Let it be empty first, and then

Comment: If the unused I/O port is suspended, a little interference from the outside may become an input signal that oscillates repeatedly. The power consumption of MOS devices basically depends on the number of flips of the gate circuit. If you pull it up, each pin will also have microamp current, so the best way is to set it as an output (of course, no other driving signals can be connected outside)

Phenomenon 4: There are so many gates left in this FPGA, so you can play it to your heart's content

Comment: The power consumption of FGPA is proportional to the number of flip-flop used and the number of flips, so the power consumption of the same type of FPGA in different circuits at different times may vary by 100 times. Minimizing the number of flip flops is the fundamental way to reduce FPGA power consumption.

Phenomenon 5: The power consumption of these small chips is very low, so it is unnecessary to consider

Comments: It is difficult to determine the power consumption of a chip that is not too complex internally. It is mainly determined by the current on the pin. An ABT16,244 consumes less than 1 mA without a load, but its indicator is that each pin can drive a load of 60 mA (such as matching a resistance of tens of ohms). That is, the maximum power consumption of a full load can reach 60 * 16=960mA. Of course, the power supply current is so large that the heat falls on the load.

Phenomenon 6: There are so many control signals in the memory. I only need to use OE and WE signals on this board. Just ground the chip selection, so that the data will come out much faster during the read operation.

Comment: The power consumption of most memories will be more than 100 times greater when the chip selection is valid (regardless of OE and WE) than when the chip selection is invalid. Therefore, CS should be used to control the chip as much as possible, and the width of the chip selection pulse should be shortened as much as possible when other requirements are met.

Phenomenon 7: Why are these signals overshoot? As long as the match is good, it can be eliminated

Comments: Except for a few specific signals (such as 100BASE-T and CML), there are overshoots. As long as they are not very large, they do not need to be matched, even if the matching is not the best. For example, the output impedance of TTL is less than 50 ohms, and some even 20 ohms. If such a large matching resistance is also used, the current will be very large, the power consumption will be unacceptable, and the signal amplitude will be too small to use. In addition, the output impedance of general signals at high output level and low output level is not the same, and there is no way to achieve complete matching. Therefore, the matching of TTL, LVDS, 422 and other signals is acceptable as long as overshoot is achieved.

Phenomenon 8: Reducing power consumption is a matter for hardware personnel, not software

Comment: The hardware is just a stage, but the software is the singer. The access to almost every chip on the bus and the overturning of every signal are almost controlled by the software. If the software can reduce the number of accesses to external memory (use more register variables, use more internal CACHE, etc.) Timely response to interrupts (interrupts are usually low level and have pull-up resistors) and other specific measures for specific boards will contribute greatly to reducing power consumption.

3： System efficiency

Phenomenon 1: The 100M main frequency CPU can only handle 70% of the data, and the 200M main frequency CPU will be fine

Comment: The processing capacity of the system involves a variety of factors. The bottleneck of communication business is usually in the memory. No matter how fast the CPU is, it is futile for external access.

Phenomenon 2: If the CPU uses a larger CACHE, it should be faster

Comment: The increase of CACHE does not necessarily lead to the improvement of system performance. In some cases, turning off CACHE is faster than using CACHE. The reason is that the data moved to CACHE must be reused for many times to improve the system efficiency. Therefore, in the communication system, only the instruction CACHE is normally opened, and even if the data CACHE is opened, it is only limited to part of the storage space, such as the stack. At the same time, it also requires that the program design should take into account the capacity and block size of CACHE, which involves the length and jump range of the key code loop. If a loop is just a little larger than CACHE, and it is repeated, it will be disastrous.

Phenomenon 3: Are so many tasks interrupted or queried? It's better to interrupt quickly

Comment: Interruption is real-time, but not necessarily fast. If there are too many task interruptions, the system will crash soon after this happens. If the number of tasks is large but frequent, the CPU spends a lot of energy on the overhead of incoming and outgoing interrupts. The system efficiency is extremely low. If the query method is used, the efficiency can be greatly improved, but sometimes the query cannot meet the real-time requirements. Therefore, the best way is to query in the interrupt, that is, to finish all the accumulated tasks in the next interrupt before exiting.

Phenomenon 4: The timing of the memory interface is the default configuration of the manufacturer and does not need to be modified

Comment: The default values set by BSP for the memory interface are based on the most conservative parameters. In practical applications, the parameters such as bus operating frequency and waiting period should be reasonably adjusted. Sometimes reducing the frequency can improve the efficiency. For example, when the access cycle of RAM is 70ns and the bus frequency is 40M, the access time of three cycles, namely 75ns, can be set; If the bus frequency is 50M, it must be set to 4 cycles, but the actual access time slows down to 80ns.

Phenomenon 5: If one CPU can't handle it, two distributed processors will be used, and the processing capacity can be doubled

Comments: For moving bricks, two people should be twice as efficient as one; For painting, more people can only help. The use of several CPUs can only be determined after more understanding of the business. The cost of coordination between the two CPUs should be minimized to make 1+1 as close as possible to 2, and never less than 1.

Phenomenon 6: This CPU is equipped with a DMA module. It must be fast to use it to move data

Comment: The real DMA is that the hardware preempts the bus and starts the devices at both ends at the same time, reading here and there in a cycle. However, many DMAs embedded in the CPU are just simulations. Before starting each DMA, a lot of preparation work (setting the starting address and length, etc.) needs to be done. During transmission, it is often read into the chip for temporary storage first, and then written out. That is, moving data once requires two clock cycles, which is faster than moving data by software (no instruction fetching, no cycle hopping and other additional work). However, if only a few bytes are moved at a time, a lot of preparation work needs to be done, Generally, function calls are also involved, which is not efficient. Therefore, this DMA is only applicable to large data blocks.

4： Signal integrity

Phenomenon 1: These signals have been simulated, absolutely no problem

Comment: The simulation model cannot be the same as the real object. Even the real objects processed in different batches are different, let alone the model. In addition, the actual situation varies greatly, and the simulation cannot enumerate all possibilities, especially crosstalk. A lesson once learned is that packets of a board with a specific length are easy to lose. The final reason is that the value of the length field is 0xFF. When this data appears on the bus, it interferes with adjacent WE signals, resulting in no write to RAM. Other data will also interfere with WE, but the interference is within the acceptable range. However, when the 8-bit bus is simultaneously from 0 to 1, nearby signals will be overwhelmed. The conclusion is that the simulation results are only for reference, and enough margin should be left.

Phenomenon 2: 100M data bus should be considered as high frequency signal. As for the clock signal frequency of 8K, it is not a problem

Comment: The value of the data bus is usually sampled by a certain edge of the control signal or clock signal. As long as the edge is maintained with sufficient setup time and hold time, the interference or overshoot outside this range will not have much impact (of course, the overshoot should not exceed the maximum voltage value that the chip can withstand), but no matter how low the frequency of the clock signal is (in fact, the spectrum range is very wide), Its edge is the key, and its monotonicity must be guaranteed, and the jump time must be within a certain range.

Phenomenon 3: Since it is a digital signal, the steeper the edge is, of course, the better

Comments: The steeper the edge is, the wider the spectral range is, and the greater the energy of the high-frequency part is; The higher the frequency, the easier it is to radiate signals (for example, microwave radios can be made into mobile phones, while long wave radios cannot be made in many countries), and the easier it is to interfere with other signals, while the transmission quality on the wires becomes worse. Therefore, those who can use low-speed chips should try to use low-speed chips,.

Phenomenon 4: To ensure a clean power supply, more decoupling capacitors are better

Comments: In general, the more decoupling capacitors, the more stable the power supply will be, but too many also have negative factors: waste of cost, difficult wiring, too much power on impulse current, etc. The key to the design of the decoupling capacitor is to select the right capacity and place it. The general chip manual has a reference for the design of the decoupling capacitor. It is better to follow the manual.

Phenomenon 5: Signal matching is really troublesome. How can we match it well?

Comment: The general principle is that when the transmission time of the signal on the wire exceeds its jump time, the reflection of the signal becomes important. The reflection of the signal is caused by the non-uniformity of the line impedance. The purpose of matching is to make the impedance of the drive end, load end and transmission line close, but whether the matching is good depends on the topology of the signal line on the PCB. A branch, a via, a corner, a connector on the transmission line, and the change of the distance between different positions and the ground wire will change the impedance, Moreover, these factors will make the reflected waveform extremely complex and difficult to match. Therefore, high-speed signals only use the point-to-point method to minimize problems such as vias and corners. PCB assembly, PCB design, PCB processing manufacturers introduce PCB design experience of a hardware master.