Expert solutions to high-speed circuit board design methods Part 1

Circuit board assembly, circuit board processing manufacturers explain high-speed circuit board design methods Part I

1. How to realize the difference distribution line of high-speed clock signal? How to solve the problem of signal integrity in high-speed circuit design? How is the difference distribution line realized? For the clock signal line with only one output terminal, how to realize the difference distribution line?

Expert answer:

Signal integrity is basically a problem of impedance matching. The factors that affect impedance matching include the structure of the signal source and output impedance, the characteristic impedance of the routing, the characteristics of the load side, and the topology architecture of the routing. The solution is to terminate and adjust the topology of routing.

Two points should be noted in the wiring of differential pairs. One is that the length of the two lines should be the same as far as possible, and the other is that the distance between the two lines (the distance is determined by the differential impedance) should always remain unchanged, that is, they should remain parallel. There are two parallel ways. One is that two lines walk on the same side by side, and the other is that two lines walk on the upper and lower adjacent layers. Generally, the former has many side by side implementations.

It is meaningful to use differential distribution lines only if both the signal source and the receiver are differential signals. Therefore, the difference distribution line cannot be used for the clock signal with only one output terminal

2. High speed differential signal wiring When the pcb board is close to the parallel high-speed differential signal line pair, in the case of impedance matching, due to the mutual coupling of the two lines, it will bring many benefits. However, some people think that this will increase the signal attenuation and affect the transmission distance. Is that so? Why? On the evaluation boards of some large companies, I found that some high-speed cabling is as close and parallel as possible, while others intentionally make the distance between two lines vary from one another. I don't know which one is better. My signal is above 1GHz and the impedance is 50 ohms.

When using software to calculate, is the differential line pair also calculated in 50 ohms? Or 100 ohms? Can a matching resistance be added between differential line pairs at the receiving end? thank you!

Expert answer:

One reason for the attenuation of high-frequency signal energy is the conductor loss, including skin effect, and the other is the dielectric loss of dielectric materials. When analyzing the transmission line effect in electromagnetic theory, we can see the influence of these two factors on signal attenuation. The coupling of differential lines will affect their respective characteristic impedance and become smaller. According to the voltage divider principle, this will make the voltage of the signal source to the line smaller. As for the theoretical analysis of signal attenuation due to coupling, I have not seen it, so I cannot comment on it.

The wiring of differential pairs should be properly close and parallel. The so-called appropriate approach is because this distance will affect the value of differential impedance, which is an important parameter for designing differential pairs. The need for parallelism is also due to the need to maintain the consistency of differential impedance. If the two lines are either far or near, the differential impedance will be inconsistent, which will affect signal integrity and timing delay.

The differential impedance is calculated as 2 (Z11 - Z12), where Z11 is the characteristic impedance of the routing itself, and Z12 is the impedance generated by the coupling between two differential lines, which is related to the line spacing. Therefore, when the differential impedance is designed to be 100 ohms, the characteristic impedance of the wiring itself must be slightly greater than 50 ohms. As for the size, it can be calculated by simulation software. The matching resistance between differential line pairs at the receiving end is usually added, and its value should be equal to the value of differential impedance. This will improve the signal quality.

3. How to deal with some theoretical conflicts in actual wiring. In actual wiring, many theories conflict with each other; For example:

1。 Processing multiple A/D ground connections: theoretically, they should be isolated from each other. However, in the actual miniaturized and high-density cabling, the space limitation or absolute isolation will lead to too long small signal analog ground wiring, which is difficult to achieve the theoretical connection. My approach is to divide the A/D function module into a complete island, and the A/D of the function module is connected to this island. Then connect the isolated island and "big" through the channel. I wonder if this is correct?

2。 Theoretically, the connection between the crystal oscillator and the CPU should be as short as possible. Due to the structural layout, the connection between the crystal oscillator and the CPU is long and thin, so it is disturbed and unstable. How to solve this problem from the wiring? There are still many problems like this, especially when EMC and EMI are considered in high-speed PCB wiring. There are many conflicts and headaches. How can we solve these conflicts? thank you very much!

Expert answer:

A Basically, it is right to divide and isolate the analog/digital signal. It should be noted that the signal wiring should not cross the moit, and the return current path of the power supply and signal should not become too large.

The B crystal oscillator is an analog positive feedback oscillation circuit. To have a stable oscillation signal, it must meet the specifications of loop gain and phase. The oscillation specification of this analog signal is very easy to be interfered. Even if ground guard traces are added, it may not be able to completely isolate the interference. Moreover, if it is too far away, the noise on the ground plane will also affect the positive feedback oscillation circuit. Therefore, the distance between the crystal oscillator and the chip must be as close as possible.

C Indeed, there are many conflicts between high-speed cabling and EMI requirements. However, the basic principle is that some electrical characteristics of the signal cannot meet the specifications due to the resistance capacitance or ferrite beam added by EMI. Therefore, it is better to solve or reduce the EMI problem by using the techniques of routing and PCB stacking, such as high-speed signal routing to the inner layer. Finally, use resistance capacitor or ferrite beam to reduce the damage to the signal.

4. Anti interference in the analog part Some systems often have A/D, ask: to improve the anti-interference, in addition to analog and digital separation, only connect at one point of the power supply, and thicken the ground wire and power line, I hope experts give some good advice and suggestions!

Expert answer:

In addition to the isolation of the ground, attention should also be paid to the power supply of the analog circuit. If the power supply is shared with the digital circuit, it is better to add a filter circuit. In addition, the digital signal and analog signal shall not be staggered, especially the place where they are separated (moot).

5. Automatic wiring of high-speed signal In order to maximize the quality of high-speed signals, we are used to manual wiring, but the efficiency is too low. The automatic router can not monitor the winding mode of key signals, the number and position of vias, etc. Manual routing of key signals and automatic routing will reduce the routing rate of automatic routing. Moreover, the adjustment of automatic routing results means more routing work. How to balance the above contradictions and use excellent routing devices to help complete high-speed signal routing?

Expert answer:

Most automatic routing devices with strong routing software now have set constraints to control the winding mode and the number of vias. The setting items of winding engine capacity and constraints of various EDA companies are sometimes far from each other. For example, whether there are enough constraints to control the way of serpentine winding, and whether the distance between differential pairs can be controlled. This will affect whether the routing method of automatic routing can conform to the designer's idea. In addition, the difficulty of manually adjusting the wiring is also absolutely related to the ability of the winding engine. For example, the pushing ability of routing, the pushing ability of vias, and even the pushing ability of routing to copper coating, etc. Therefore, the solution is to choose a router with strong winding engine.

6 About test coupling Is there any specification for the design of test coupon? How to design a test coupler according to the actual situation of the board? What problems need attention? thank you!

Expert answer:

The test coupler is used to measure whether the characteristic impedance of the PCB produced meets the design requirements with TDR (Time Domain Reflectometer). Generally, the impedance to be controlled includes single wire and differential pair. Therefore, the routing line width and line spacing (when there is differential alignment) on the test coupler should be the same as the lines to be controlled. The most important is the position of the grounding point during the measurement. In order to reduce the inductance of the ground lead, the place where the TDR probe is grounded is usually very close to the place where the signal is measured. Therefore, the distance and method between the measuring signal point on the test coupler and the grounding point should conform to the probe used.

7. About the copper grounding problem in the blank area of the signal layer in the high-speed PCB design In the design of high-speed PCB, the blank area of the signal layer can be coated with copper. Is it better to ground copper on multiple signal layers, or to half ground and half power?

Expert answer:

Generally, the copper coating in the blank area is mostly grounded. It is only necessary to pay attention to the distance between the copper coating and the signal line when copper is applied beside the high-speed signal line, because the copper coating will reduce the characteristic impedance of the line. Also pay attention not to affect the characteristic impedance of other layers, such as in the structure of dual stripline.

8. Characteristic impedance Thank you for answering my last question. Last time, you said that the power plane and ground plane are basically metal planes, so they have shielding effects on electric and magnetic fields. Can I use the microstrip line model to calculate the characteristic impedance of the signal lines on the power plane? Can the signal between the power supply and the ground plane be calculated using the stripline model?

Expert answer:

Yes, both the power plane and the ground plane must be considered as reference planes when calculating the characteristic impedance. For example, the four layer board: top layer - power layer - stratum - bottom layer. At this time, the model of the characteristic impedance of the top layer wiring is the microstrip line model with the power plane as the reference plane.

9. High speed signal line matching In the layout of high-speed boards (such as P4 motherboards), why do high-speed signal lines (such as cpu data and address signal lines) need to be matched? What hidden danger will it bring if it does not match? What factors determine the matching length range (i.e. delay difference of signal line) and how to calculate it?

Expert answer:

The main reason for matching the characteristic impedance of routing is to avoid the reflection caused by high-speed transmission line effect affecting signal integrity and delay time. That is to say, if there is no match, the signal will be reflected to affect its quality.

The length range of all routes is determined according to timing requirements. There are many factors that affect the signal delay time, and the routing length is only one of them. P4 requires that the length of some signal lines in a certain range is the timing margin calculated according to the transmission mode (common clock or source synchronous) used by the signal, and a part of it is allocated to the allowable error of the routing length. As for the time sequence calculation of the above two modes, it is not convenient to elaborate here due to time and space limitations. Circuit board assembly, circuit board design, and circuit board processing manufacturers explain high-speed circuit board design methods.