Amplifier PCB wiring skills

In the circuit design process, application engineers often neglect the layout of printed circuit boards (PCB). A common problem is that the circuit schematic is correct, but it doesn't work, or only operates at low performance. I'll show you how to properly lay out the circuit board of an op-amp to ensure its functionality, performance, and robustness.

Recently, I worked with an intern on the OPA191 operational amplifier in the same phase configuration with a gain of 2V/V, a load of 10kΩ and a supply voltage of +/-15V. Figure 1 shows the schematic diagram of the design.

An OPA191 schematic diagram with in-phase configurations Indicates the OPA191 schematic diagram

I asked the intern to make the boards for the design, gave him general instructions on PCB layout (e.g., minimize the circuit boards' wiring paths, keep the components as close together as possible to minimize the board's footprint)) space), and then left him to design his own. How hard was the design process? It's just a few resistors and capacitors, isn't it? Figure 2 shows his initial attempt at a layout. The red line is the path to the top of the board, and the blue line is the bottom path

The first layout attempt

Seeing his first attempt at layout, I realized that the board layout wasn't as intuitive as I thought; I should at least give him more detailed instructions. He did exactly what I suggested in the design: shorten the wiring path and pack the parts close together. However, in order to reduce the parasitic impedance of the board and optimize its performance, this layout still has a lot of room for improvement.

The next step is to improve the layout. The first improvement we made was to move resistors R1 and R2 to the inverting pin of the OPA191 (pin 2); This helps reduce stray capacitance of the inverting pin. The inverse pin of an operational amplifier is a high-impedance node and therefore has high sensitivity. Longer routing paths can be used as conductors to couple high-frequency noise into the signal chain. The PCB capacitance on the inverting pin can cause stability problems. Therefore, the contact on the inverting pin should be as small as possible.

Moving R1 and R2 to pin 2 allows the load resistor R3 to rotate 180 degrees, thus bringing the decoupling capacitor C1 closer to the positive power pin of the OPA191 (pin 7). It is important that the decoupling capacitor be as close to the power supply pin as possible. If the routing path between the decoupling capacitor and the power pin is long, the inductance of the power pin will increase, decreasing performance.

Improve the placement of parts of the layout

After moving the part to its new location, you can still make some other improvements. You can widen the path to reduce the inductance, which corresponds to the size of the pad to which the path is attached. The top and bottom ground of the board can also be perfused to create a reliable low-impedance path for return current.

The next time you layout a printed circuit board, it is recommended that you follow the following layout conventions:

1. Minimize the connection of inverting pins.

2. Place the decoupling capacitor as close to the power pin as possible.

3. If multiple decoupling capacitors are used, place the smallest one closest to the power supply pin.

4. Do not place a hole between the decoupling capacitor and the power pin.

5. Expand the route path as much as possible.

In the previous article, we discussed the proper layout of instrument amplifier (OP-amp) PCBS and provided a series of good layout practices for reference. Next, we'll explore common mistakes when arranging instrumentation amplifiers (INA), and then show how to properly arrange INA PCBS.

INA is used in applications that require amplification of differential voltages, such as measuring the voltage at both ends of a shunt resistor in high-end current detection applications. Figure 5 shows the schematic diagram of a typical single-supply high-side current detection circuit.

5 The differential voltage is measured by RSHUNT, where R1, R2, C1, C2, and C3 are used to provide common-mode and differential mode filtering, R3 and C4 provide output filtering for the U1 INA, and U2 is used to buffer the INA reference pins. R4 and C5 are used to form a low-pass filter that minimizes the noise introduced into the INA reference pins by the operational amplifier.

While the schematic layout in Figure 5 looks intuitive, it is easy to make mistakes in a PCB layout, resulting in reduced circuit performance. Figure 6 shows three common errors that workers make when examining INA layouts.

INA universal PCB layout

As can be seen from the figure above, the first error is to measure the differential voltage Rshunt through the resistance. It can be seen that the Rshunt to R2 line is shorter, so its resistance is smaller than that of Rshunt to R1. This difference in line impedance may introduce input bias current into the INA, resulting in a differential voltage on the U1 input side. Since the INA's task is to amplify the differential voltage, unbalanced circuits on the input side can cause errors. Therefore, you need to ensure that the INA input lines are balanced and as short as possible.

The second error is related to the INA gain setting resistor Rgain. The length of the U1 pin to the Rgain pad is longer than it needs to be, resulting in additional resistance and capacitance. Since the gain depends on the resistance between the INA gain setting pin, pin 1, and pin 8, additional resistance can bring the wrong target gain. Since the gain setting pins of the INA are connected to the feedback portion in the INA, additional capacitance can cause stability problems. Therefore, make sure that the line connecting the gain setting resistance is as short as possible.

Then, it may be necessary to improve the position of the buffer circuit reference pins. The reference pin buffer circuit is away from the reference pin, which may increase the resistance of the reference pin, causing noise or other signals to be coupled into the line. The additional resistance on the reference pin may reduce the high common-mode rejection ratio (CMRR) provided by most InAs. Therefore, the reference pin buffer circuit should be placed as close to the INA reference pin as possible.

The layout with these three errors corrected is shown.

In Figure 7, you can see that R1 and R2 have the same length of wire to the shunt resistor, and a Kelvin connection is used. INA pin gain setting resistance as short as possible, reference buffer circuit as close as possible to the reference pin.

If you want to lay out PCBS for INA in the future, be sure to follow these guidelines:

1. Ensure that all lines at the input end are completely balanced;

2. Reduce the line length and minimize the capacitance on the gain setting pin;

3. Arrange the reference buffer circuit as close to the INA reference pin as possible;

4, decoupling capacitor as close as possible to the power supply pin layout;

5. Cover at least one layer of solid ground plane;

6. Do not sacrifice good layout for electronic components using silk screen printing;

7. Follow the guidelines outlined in the first part of this article.