Try to solve the noise problem from the PCB layout and wiring

Noise is one of the four words every circuit board designer hears. It often takes hours of laboratory testing to find the culprit, only to find that the noise is caused by the improper layout of the switching power supply. Resolving such issues may require the design of a new layout, resulting in product delays and increased development costs.

This article provides guidance on printed circuit board (PCB) layout and wiring to help designers avoid such noise problems. The example switching regulator layout uses a dual channel synchronous switching controller ADP1850. The first step is to determine the current path of the regulator. The current path then determines the location of the device in this low noise layout routing design.

PCB layout and wiring guide

Step 1: Determine the current path

In a switching converter design, high current paths and low current paths are very close to each other. AC (AC) paths carry spikes and noise, high DC (DC) paths produce considerable voltage drops, and low current paths tend to be sensitive to noise. The key to proper PCB layout is to determine the critical path, then arrange the components, and provide enough copper area so that high current does not destroy low current. Poor performance is ground bounce and noise injection into the IC and the rest of the system.

Low-value, low-amplitude signal paths, such as compensation and feedback devices, are sensitive to noise. These paths should be kept far away from shutdown points and power supply devices to avoid injecting interference noise.

Step 2: Lay out the physical plan

PCB physical planning (floor plan) is very important. The current loop area must be minimized, and the power supply devices must be rationally arranged to make the current flow smoothly and avoid sharp corners and narrow paths. This will help reduce the parasitic capacitance and inductance, thus eliminating grounding bounce.

Step 3: Power supply devices -- MosFETs and capacitors (input, bypass, and output)

The current waveform at the top and bottom power switches is a pulse with very high delta I/ delta t. Therefore, the path connecting the switches should be as short as possible to minimize noise picked up by the controller and noise transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FeTs on one side of the PCB, it is best to rotate the two FeTs in opposite directions SO that the switching node is on the side of the pair of FETs and the high end leakage current is bypassed to the low end source with a suitable ceramic bypass capacitor. It is important to place the bypass capacitor as close to the MOSFEts as possible (see Figure 2) to minimize inductance around the loop that passes through the FETs and the capacitor.

The placement of input bypass capacitors and input large capacitors is essential to control grounding bounce. The negative connection of the output filter capacitor should be as close to the source of the low-end MOSFETs as possible, which helps to reduce the loop inductance that causes ground bounce. Cb1 and Cb2 in Figure 2 are ceramic bypass capacitors. The recommended values for these capacitors range from 1 μF to 22 μF. For high current applications, an additional filter capacitor with a larger value should be shunt in parallel.

Heat dissipation is considered and connected to strata

Under heavy-duty conditions, the equivalent series resistance (ESR) of the power mosFETs, inductors, and large capacitors produce a significant amount of heat. For effective heat dissipation, a large area of copper is placed under the power component.

The heat dissipation effect of multilayer PCB is better than that of 2-layer PCB. To improve heat dissipation and electrical conductivity, a 2-ounce thickness of copper should be used on top of a standard 1-ounce copper layer. It also helps to have multiple PGND layers connected together through holes.

The negative ends of all power components (such as low-end switches, bypass capacitors, input and output capacitors, etc.) are connected to the PGND layer, which carries high current.

The pressure drop within the GND layer can be so large that it affects output accuracy. Walk through a wide line will AGND layer connected to the output capacitance of the negative side, can significantly improve the output precision and load regulation.

Current detection path

In order to avoid the accuracy drop caused by interference noise, the current detection path layout of the current mode switch regulator must be appropriate. Dual-channel applications in particular need to be more focused on eliminating any cross-talk between channels.

The dual-channel step-down controller ADP1850 uses the on-resistance RDS(ON) of the low-end mosfeTs as part of the control loop architecture. This architecture detects the current flowing through the low end mosFETs between the SWx and PGNDx pins. Ground current noise in one channel may be coupled to adjacent channels. Therefore, it is important to make SWx and PGNDx routes as short as possible and place them close to the MOSFETs for accurate current detection. Connections to SWx and PGNDx nodes must be made using Kelvin detection technology.

In contrast, for dual-channel voltage mode controllers such as ADP1829, PGND1 and PGND2 pins are directly connected to the PGND layer through the through-hole.

Feedback and current limiting detection paths

Feedback (FB) and current limiting (ILIM) pins are low signal level inputs, and as such, they are sensitive to capacitive and inductive noise interference. FB and ILIM should avoid routing near high δI/δt. Be careful not to let the cable form a loop, resulting in the increase of bad inductance. Adding a small MLCC decoupling capacitor (e.g. 22 pF) between the ILIM and PGND pins helps to further filter the noise.

Switching node

In a switched regulator circuit, the switch (SW) node is the noisiest place because it carries a lot of AC and DC voltage/current. This SW node requires a large area of copper to minimize the resistive pressure drop. Placing the MOSFETs and inductors close to each other on a copper layer minimizes series resistance and inductance.

Applications that are more sensitive to electromagnetic interference, switching node noise, and ringing oscillations may use a small buffer. The buffer consists of a resistor and a capacitor in series

Grid driver path

Grid drive wiring (DH and DL) is also dealt with and tends to produce ringing oscillations and overshoot. These routes should be as short as possible. Direct wiring is preferred, avoiding the use of feed through holes. If pass holes must be used, use two pass holes per route to reduce peak current density and parasitic inductance.

Placing a small resistor (about 2 to 4 Ω) in series on the DH or DL pins slows down the grid drive, which also reduces grid noise and overshoot. Alternatively, a resistor can be connected between the BST and the SW pin. Preserving space with a 0 ohm grid resistance during layout improves flexibility for later evaluation. Increased gate resistance will prolong the rise and fall time of gate charge, resulting in higher switching power loss of the MOSFET.