JEDEC distinguishes ESD at the component level and system level

PCB designers need to think about what happens at the system level because this is the area they can control.

This figure shows where a system-level ESD may occur. Exposed IO and connectors are obvious locations where ESD events can propagate electrical impulses into the system and potentially damage components.

A system-level ESD event occurs within a PCBA and may affect multiple components, resulting in one of the following outcomes:

There is no problem with the system continuing to work

The system has a failure/lock (soft failure), but no physical failure.

Physical damage to the system (hard failure)

Various industry standards beyond the IPC standard require the ability of equipment to withstand electrostatic discharge. The specific test method depends on the standard used for your product (e.g. IEC 62368-1/IEC 61000, ISO 10605 for automobiles, DO-160 for avionics, etc.). Refer to the relevant safety standards for your product and industry to determine the level of ESD protection required for your product.

Environmental stress screening (ESS) tests

These tests are designed to closely simulate the ideal deployment environment for the appliance. ESS testing may involve the application of thermal cycling, drop testing, vibration testing, thermal/mechanical shock testing, and any other environmental or mechanical exposure to which the equipment is expected to be subjected during operation. More specialized testing methods might involve crash testing, pressure and humidity testing, or even altitude testing. Highly reliable systems need to withstand all of these environmental factors during electrical operation, so multiple tests are often required to ensure reliability.

Functional tests are also performed before, during, and after these tests to fully determine whether the design will fail and whether functionality will be compromised. These tests not only looked at electrical stress, but also verified functionality in a variety of pressure situations, which could include electrical overstress and even ESD. Because this is usually a combination of professional tests that need to be performed, the rigorous evaluation is performed by the design team rather than the manufacturer.

Accelerated life test

This refers to a set of possible tests designed to determine the approximate useful life of the new equipment. Accelerated life tests are often lumped together as "burn-in tests," although there are many variations on these tests. The accelerated life test can be divided into the following aspects:

Burn-in testing: A method of using statistical techniques to determine which components and/or components will fail early.

High Accelerated Life Testing (HALT) : The goal here is to stress the device until it fails during severe overrun. This simulates excessive operation under real environmental conditions where the device is deployed.

Highly Accelerated Stress testing (HAST) : Similar to HALT, in that designs are stressed to complete failure.

Highly accelerated stress testing (HASS) : Use the same ambient stress as HASS, but at a lower level, and usually after completing a full HALT test.

Any of these life/stress tests can be carried out in accordance with the other test methods described above, provided appropriate testing rooms and equipment are available. This combination of tests can be highly specialized, but they are critical to determining the useful life of electronics and identifying failure mechanisms.

Fault analysis

These electrical stress tests are designed to determine the limits of the equipment and to assess whether it can withstand the environmental conditions during operation. If you find that the design cannot withstand the expected stress level and fails, some failure analysis is required to determine the root cause of the equipment failure. Failures can occur at the component level, board level, or both, so some forensic investigation is required to determine the failure mechanism.

For modern high-speed designs, the preferred grounding strategy is usually to use one or more continuous connecting strata on the inner layer. This provides better EMI protection and ensures a clear signal path, which improves overall signal integrity. Avoid wiring in any ground gaps in areas where the ground plane is disconnected due to a unique circuit board profile or feature. Without contiguous and adjacent ground planes for the signal to use as a clear return path, your design can produce a lot of undesirable noise. Here are some power and ground floor guidelines to keep in mind:

The grounding layer needs to be adjacent to the signal layer in the board stack with high speed wiring. This will help shield the high-speed wiring from interference and provide a good reference plane for the signal return path.

Use heat dissipation pads and carefully manage the power supply and ground connections to the plane. Cushioning spokes must be wide enough to withstand high currents while eliminating the opportunity for these connections to act as radiators.

Carefully plan the power connections and split the power plane to ensure adequate delivery of power to all connected components throughout the board.