Ways to ensure the integrity of PCB design signal

Signal integrity in PCB design refers to the quality of the signal on the signal line, that is, the ability of the signal to respond with correct timing and voltage in the circuit. If the signal in the circuit can reach the receiver with the required time sequence, duration and voltage amplitude, it can be determined that the circuit has good signal integrity. On the contrary, when the signal fails to respond normally, the problem of signal integrity arises.

With the use of high-speed devices and the increasing design of high-speed digital systems, system data rate, clock rate and circuit density are increasing. In this design, the system has fast slope transient and high operating frequency, and cables, interconnects, printed boards (PCBs) and silicon chips will show different behaviors from low-speed design, that is, signal integrity problems will occur.

The problem of signal integrity can lead to or directly lead to such problems as signal distortion, timing error, incorrect data, address, control line and system error, and even make the system collapse, which has become a very noticeable problem in high-speed product design. This paper first introduces the problem of PCB signal integrity, then describes the steps of PCB signal integrity, and finally introduces how to ensure the signal integrity of PCB design.

PCB signal integrity problems include:

The signal integrity problems of PCB mainly include signal reflection, crosstalk, signal delay and timing error.

1. Reflection: When the signal is transmitted on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB does not match the source impedance or load impedance of the signal, the signal will reflect, causing the signal waveform to overshoot, undershoot and the resulting ringing. Overshoot refers to the first peak (or valley) of signal jump, which is the additional voltage effect above the power level or below the reference ground level; Undershoot refers to the next valley (or peak) of signal jump. Excessive overshoot voltage will often impact the device for a long time, which will cause damage to the device. Downrush will reduce the noise tolerance, and ringing will increase the time required for signal stability, thus affecting the system timing.

2. Crosstalk: In PCB, crosstalk refers to the undesirable noise interference caused by electromagnetic energy on adjacent transmission lines through mutual capacitance and mutual inductance coupling when signals propagate on transmission lines. It is caused by the interaction of electromagnetic fields caused by different structures in the same area. Mutual capacitance causes coupling current, which is called capacitive crosstalk; The mutual inductance causes coupling voltage, which is called inductive crosstalk. On a PCB, crosstalk is related to the length of wiring, the distance between signal lines, and the condition of the reference ground plane.

3. Signal delay and timing error: The signal is transmitted at a limited speed on the wire of the PCB, and the signal is sent from the drive end to the receiving end. There is a transmission delay between them. Excessive signal delay or mismatched signal delay may lead to timing errors and confusion of logic device functions. High speed digital system design and analysis based on signal integrity analysis can not only effectively improve product performance, but also shorten product development cycle and reduce development costs. With the development of digital system towards high-speed and high-density, it is urgent and necessary to master this design tool. With the continuous improvement of the model and calculation analysis algorithm of signal integrity analysis, the digital system design method using signal integrity for computer design and analysis will be widely and comprehensively applied.

Steps of PCB signal integrity:

1. Preparation before design

Before the design, we must first think about and determine the design strategy, so as to guide the work such as the selection of components, process selection and cost control of circuit board production. As far as SI is concerned, it is necessary to conduct research in advance to form planning or design criteria, so as to ensure that there are no obvious SI problems, crosstalk or timing problems in the design results.

2. Stacking of circuit boards

Some project groups have great autonomy in determining the number of PCB layers, while others do not. Therefore, it is important to know where you are. Other important questions include: What is the expected manufacturing tolerance? What is the expected insulation constant on the board? What is the allowable error of line width and spacing? What is the allowable error of the thickness and spacing between the ground plane and the signal layer? All of this information can be used during the pre wiring phase.

Based on the above data, you can select cascading. Note that almost every PCB inserted into other circuit boards or backplanes has thickness requirements, and most circuit board manufacturers have fixed thickness requirements for different types of layers they can manufacture, which will greatly constrain the number of final layers. You may want to work closely with the manufacturer to define the number of cascades. Impedance control tools should be used to generate target impedance ranges for different layers, taking into account the manufacturer's manufacturing tolerances and the effects of adjacent wiring.

Under the ideal condition of complete signal, all high-speed nodes should be wired in the impedance control inner layer (such as stripline). To optimize the SI and keep the circuit board decoupled, the ground/power layers should be laid in pairs as far as possible. If there is only one connecting stratum/power layer, you have to make do with it. If there is no power layer at all, you may encounter SI problems by definition. You may also encounter situations where it is difficult to simulate or simulate the performance of a circuit board before the return path of the signal is defined.

3. Crosstalk and impedance control

Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal lines. The coupling analysis of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel wiring length) between signal lines or between various signal lines. For example, if you want to limit the crosstalk from the clock to the data signal node to within 100mV, but want the signal wiring to remain parallel, you can find the minimum allowable distance between signals on any given wiring layer through calculation or simulation. At the same time, if the design includes nodes with important impedance (or clock or dedicated high-speed memory architecture), you must place the cabling on one layer (or several layers) to obtain the desired impedance.

4. Important high-speed nodes

Delay and time delay are the key factors that must be considered in clock routing. Because of strict timing requirements, such nodes usually must use termination devices to achieve the best SI quality. These nodes shall be determined in advance, and the time required for adjusting the placement and wiring of components shall be planned to adjust the pointer of signal integrity design.

5. Technology selection

Different driving technologies are suitable for different tasks. Is the signal point-to-point or one to many tapped? Is the signal output from the circuit board or left on the same circuit board? What is the allowable time delay and noise margin? As a general criterion for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason to use 500PS rise time for 50MHz clock. A 2-3NS swing rate controller must be fast enough to ensure the quality of SI and help solve problems such as output synchronous switching (SSO) and electromagnetic compatibility (EMC).

The advantages of driver technology can be found in the new FPGA programmable technology or user-defined ASIC. With these customized (or semi customized) devices, you have a lot of room to choose the drive amplitude and speed. At the initial stage of design, it is necessary to meet the requirements of FPGA (or ASIC) design time and determine the appropriate output selection, including pin selection if possible.

In this design phase, appropriate simulation models should be obtained from IC suppliers. In order to effectively cover SI simulation, you will need an SI simulation program and corresponding simulation model (possibly IBIS model).

Finally, in the pre wiring and cabling phases, you should establish a series of design guidelines, including: target layer impedance, cabling spacing, device technology, important node topology, and termination planning.

6. Pre wiring stage

The basic process of pre routing SI planning is to first define the input parameter range (driving amplitude, impedance, tracking speed) and possible topology range (minimum/maximum length, short line length, etc.), then run each possible simulation combination, analyze the timing and SI simulation results, and finally find an acceptable numerical range.

Next, the working range is interpreted as the wiring constraint of PCB wiring. Different software tools can be used to perform this type of "sweeping" preparation, and the routing program can automatically handle such routing constraints. For most users, timing information is actually more important than SI results. The interconnection simulation results can change the routing, thus adjusting the timing of the signal path.

In other applications, this process can be used to determine the layout of pins or devices that are incompatible with the system timing pointer. At this time, it is possible to completely determine the nodes that need manual routing or do not need termination. For programmable devices and ASICs, the selection of output drivers can also be adjusted to improve the SI design or avoid the use of discrete termination devices.

7. SI simulation after wiring

Generally speaking, it is difficult for SI design guidelines to ensure that there are no SI or timing problems after the actual wiring is completed. Even if the design is conducted under the guidance of the guidelines, unless you can continuously and automatically check the design, you can never guarantee that the design will fully comply with the guidelines, so problems will inevitably occur. The post wiring SI simulation check will allow to break (or change) the design rules in a planned way, but this is only necessary for cost considerations or strict wiring requirements.

8. Post manufacturing stage

Taking the above measures can ensure the SI design quality of the circuit board. After the circuit board is assembled, it is still necessary to put the circuit board on the test platform, use an oscilloscope or TDR (Time Domain Reflectometer) to measure, and compare the real circuit board with the expected simulation results. These measurements can help you improve the model and manufacturing parameters so that you can make better (less constrained) decisions in the next pre design survey.

9. Model selection

There are many articles about model selection, and engineers conducting static timing verification may have noticed that, although all data can be obtained from device data tables, it is still difficult to establish a model. On the contrary, the SI simulation model is easy to establish, but the model data is difficult to obtain. In essence, the only reliable source of SI model data is IC suppliers, who must keep tacit cooperation with design engineers. IBIS model standard provides a consistent data carrier, but the establishment of IBIS model and its quality assurance are expensive. IC suppliers still need to promote the market demand for this investment, and circuit board manufacturers may be the only demander market.

PCB design method to ensure signal integrity:

By summarizing the factors that affect signal integrity, the following aspects can be considered to better ensure signal integrity during PCB design.

(1) Circuit design considerations. It includes controlling the number of synchronous switching outputs, controlling the maximum edge rate (dI/dt and dV/dt) of each unit, so as to obtain the lowest and acceptable edge rate; Select differential signal for high output function block (such as clock driver); Terminate passive components (such as resistance, capacitance, etc.) on the transmission line to achieve impedance matching between the transmission line and the load.

(2) Minimize the routing length of parallel wiring.

(3) The components shall be placed far away from the I/O interconnection interface and other areas vulnerable to interference and coupling, and the placement interval between components shall be minimized.

(4) Shorten the distance between the signal wiring and the reference plane.

(5) Reduce wiring impedance and signal drive level.

(6) Terminal matching. Terminal matching circuit or matching element can be added.

(7) Avoid mutually parallel routing, provide sufficient spacing between the routing lines, and reduce inductive coupling.