Multi-power layer design

What if the actual route is not like this? For example, the signal line on the first layer through the hole to the 10th layer, then the loop signal had to find the grounding plane from the 9th layer, the loop current to find the nearest grounding hole (such as resistance or capacitor and other components of the grounding pin). If you happen to have one nearby, you're really lucky. If there is no such a close through hole available, the inductance will be larger, capacitance to reduce, EMI must increase.

When the signal line must leave the present pair of wiring layers to other wiring layers through the hole, the ground hole should be placed near the hole, so that the loop signal can be smoothly returned to the appropriate grounding layer. For layers 4 and 7, the signal loop will return from the power layer or ground layer (i.e., layer 5 or 6) because the capacitive coupling between the power layer and ground layer is good and the signal is easily transmitted.

Multi-power layer design

If two power layers of the same voltage source need to output high current, the circuit board should be distributed into two groups of power layers and grounding layers. In this case, an insulating layer is placed between each pair of power layer and ground layer. This gives us the desired two pairs of power busbars with equal impedances for equal currents. If the stack of power layers results in unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and EMI will increase dramatically.

If there are multiple power supply voltages with different values on the circuit board, multiple power layers are required accordingly. Remember to create separate power layers and connections for each power supply. In both cases, keep in mind the manufacturer's requirements for balanced structure when determining the position of the paired power layer and ground layer on the board.

summarize

Given that most of the circuit boards designed by engineers are traditional printed circuit boards with a thickness of 62mil and no blind or buried holes, the discussion of layering and stacking of circuit boards is limited here. The layered scheme recommended in this paper may not be ideal for boards with large thickness differences. In addition, the fabrication process of circuit boards with blind holes or buried holes is different, so the layering method in this paper is not applicable.

In circuit board design, the thickness, through hole process and the number of layers of circuit board are not the key to solve the problem. Good stacking is the key to ensure the bypass and decoupling of the power busbar, to minimize the transient voltage on the power layer or ground, and to shield the electromagnetic field of the signal and the power supply. Ideally, there should be an insulating layer between the signal routing layer and the loop grounding layer, and the spacing of the paired layers (or more than one pair) should be as small as possible. According to these basic concepts and principles, can always be designed to meet the design requirements of the circuit board. Now that the rise time of IC is already short and will be shorter, the techniques discussed in this article are essential to solving EMI shielding problems.

7, about the IC pad should be extended: SOP, PLCC, QFP packaging IC drawing PCB should be extended, PCB pad length =IC foot length ×1.5 is appropriate, so that when manual soldering iron, chip pin and PCB pad, tin three melt into one. As shown below:

8, about the width of the IC pad: SOP, PLCC, QFP packaging IC, drawing PCB should pay attention to the width of the pad, PCB on the pad a width =IC foot width (i.e. : Nom in datasheet. Value), please do not widen, ensure that b(i.e., between two pads) has enough width, so as not to cause continuous welding.

9. Do not rotate the device at any Angle: because the placement machine cannot rotate at any Angle, it can only rotate 90℃, 180℃, 270℃, 360℃. As shown in Figure B below, if the rotation is 1℃, the Angle between the device pin and the pad on the circuit board will be staggered by 1℃ after the placement machine is affixed, thus affecting the welding quality.

10. Problems that should be paid attention to when shorting adjacent pins: The shorting method in Figure a below is not conducive for workers to identify whether the pins should be connected, and it is not beautiful after welding. If the drawing is short connected according to the method of Figure b and c and solder resistance is added, the welding effect will be different: as long as each pin is not connected, the chip will have no short circuit phenomenon, and the appearance is beautiful.

11, on the bottom of the chip in the middle of the pad problem: the bottom of the chip in the middle of the pad chip drawing if according to the chip packaging picture in the middle of the pad, it is easy to cause short circuit phenomenon. It is recommended to narrow the middle pad so that the distance between it and the surrounding pin pad is increased to reduce the chance of short circuit. 12. The two devices with high thickness should not be closely packed together: as shown in the figure below, the plate layout will cause the SMT machine to encounter the previous attached device when attaching the second device, and the machine will detect danger, resulting in automatic power failure of the machine.

13. About BGA: Because the BGA package is special, the welding pad is under the chip, and the welding effect cannot be seen outside. In order to facilitate the repair, it is recommended to make two positioning holes with Hole Size:30mil on the PCB board, so as to locate the steel mesh (used to scrape the solder paste) during the repair.